Digital Design Verification

Digital Design Verification

Course Overview

One of the important phase of the Digital Integrated Chip Design Process is the Design Verification. In this phase, the functionality of the digital design is being verified to determine if it conforms to its specification through input of random stimulus and different coverage monitoring. The main tool for Design Verification is the Hardware Verification Language and it follows a specific verification design flow such as the Universal Verification Methodology (UVM). This course provides the trainees with adequate background for the theories and knowledge behind functional verification process. It also discusses the usage of SystemVerilog, as the Hardware Verification Language, and UVM in the development of the verification environment. This training will enable the trainees to design and create their own verification test bench.

Course Prerequisites

The trainees for this course are expected to have completed the "Introduction to Hardware Description Lan- guage" and "Introduction to RTL Modelling of an I2C Interface" courses offered by PIIC or equivalent course workshop offered by other institutions. The trainees are also expected to know how to use the tools for HDL compilation such as Cadence NC-Verilog and Synopsys VCS.

Lectures Overview

Lecture Topic
1Introduction to Digital Design Verification
2Verification Technologies
3Verification Planning
4High-Level Modelling
5Introduction to SystemVerilog HVL
6Architecting Testbenches
7Introduction to UVM
8Coverage Driven Random-Based Verification

Laboratory Topic
1Test Items
2Test Planning
3Interfacing DUT to the Testbench
4Building I2C Driver
5Building I2C Checker
6Building the APB-I2C scoreboard
7Virtual Sequence
8Coverage Driven Verification


AM Session: 8am to 12nn
PM Session: 1pm to 4pm
Day AM/PM Lecture Lab
1AMLecture 1
Lecture 2
Lab 1
PMLecture 3Lab 2
2AMLecture 4
PMLecture 5Lab 3
3AMLecture 6
PMLecture 7Lab 4
4AMLecture 8Lab 5
PMLab 6
Lab 7
Lab 8


Noemi Salazar
BiTMICRO Networks Intl. Inc.
Jonathan T. Delarmente
BiTMICRO Networks Intl. Inc.
John Cris F. Jardin
University of the Philippines
PIIC Staff
Philippine Institute for Integrated Circuits
Microelectronics and Microprocessors Laboratory
University of the Philippines


  • Jonathan T. Delarmente, BiTMICRO Networks Intl. Inc.

Recommended Texts

  • "Writing Testbenches Using SystemVerilog" by Janick Bergeron
  • IEEE Standard 1800-2011: SystemVerilog Unified Hardware Design, Specification, and Verification Language