RTL Modeling of an I2C Interface

Introduction to Analog IC Design

Course Overview

Small-scale digital design components can usually be implemented by describing its hardware carrying out their operations using suitable computer-aided design tools. However, large digital design circuitries or complex logic circuits can be very laborious if implemented in its primitive-level. The most possible way to design these circuits is to use the highest possible level of abstraction. This gave rise to Register Transfer Level modelling in which designers think the circuits' functionality rather than the hardware implementation. This course intends to provide knowledge to trainees on Register-Transfer Logic (RTL) modelling of digital systems with emphasis on digital interfaces. The trainees are tasked to develop an I2C controller from protocol specifications, state machine design, and its RTL implementation. The emphasis on the design methodology will enable the trainee to learn specific skills through design, verification, and synthesis of a typical digital system.

Course Prerequisites

The trainees are expected to have finished the Introduction to Verilog HDL Course offered by the PIIC or any equivalent course offered by an educational institution. The trainees must be familiar with the Verilog hardware description language (HDL). They are expected to be able to work in a Linux environment and familiar with basics of TCL scripting. Moreover, the trainees are expected to have a knowledge on how to create state machines and have basic background of digital design flow - design, synthesis, and verification using EDA tools.

Lectures Overview

Lecture Topic
1Overview of Communication Protocol
2Protocol Examples
3Algorithm State Machine
4I2C Protocol - Write Operation
5Testing the Wrapper
6I2C Protocol - Write/Read Operation
7AMBA-APB Protocol
8Arrays and Loops in Verilog
9Additional Verilog Constructs

Laboratory Topic
1ASM to RTL Conversion
2I2C Wrapper with Write Functionality Only
3Pseudocode and ASM of I2C Wrapper with Read/Write Functionality
4Implementing the I2C Wrapper with Write/Read Functionality
5Update of RTL Model for AMBA-APB Interface
6Testing Multiple I2C Masters
7Using Task and Generate Statements


AM Session: 8am to 12nn
PM Session: 1pm to 4pm
Day AM/PM Lecture Lab
1AMLecture 1
Lecture 2
PMLecture 3Lab 1
2AMLecture 4Lab 2
PMLecture 5
3AMLecture 6Lab 3
PMLab 4
4AMLecture 7
PMLecture 8Lab 5
5AMLecture 9Lab 6


Rico Jossel M. Maestro
University of the Philippines
PIIC Staff
Philippine Institute for Integrated Circuits
Microelectronics and Microprocessors Laboratory
University of the Philippines


  • Adelson N. Chua, University of the Philippines
  • Ryan M. Alocilja, University of San Carlos
  • Chris Vincent J. Densing, University of the Philippines

Recommended Texts

  • Digital Design by M. Morris Mano and Michael Ciletti
  • Verilog Digital System Design: Register Transfer Level Synthesis, Testbench, and Verication by Zainalabedin Navabi
  • I2C Bus Specication
  • AMBA APB Protocol Specication