Memory Design

Memory Design

Course Overview

Out of the numerous applications of digital integrated circuits, memory cells are perhaps the most prevalent. This is due to their importance in virtually all computing devices, from the largest supercomputer to the smallest smartphone. In order to develop these memory cells, proficiency in logic families other than CMOS is required. This introductory course is intended for trainees who have mastered the construction of CMOS logic gates, as well as their optimization through the use of logical effort. Trainees taking this course will first be introduced to logic families vital to the development of memory cells, such as pass transistor logic and ratioed transistor logic. Using their knowledge of these logic families, trainees will then be instructed on the process of developing an SRAM memory cell, and will finally develop such a cell on their own as a culmination of the course and an application of the concepts taught.

Course Prerequisites

The trainees for this course are expected to have completed the Introduction to Full Custom Digital IC Design Course offered by PIIC or any equivalent course/workshop offered by any institution. The trainees for this course are expected to have taken electronics courses covering semiconductor device physics i.e. diodes and bipolar junction transistors. Moreover, the trainees are expected to have strong background on circuit analysis of passive and active devices. A background on linear systems analysis is also required. The trainees are also expected to have experience in schematic entry and circuit simulations using Cadence Virtuoso or Synopsys Custom Designer.

Lectures Overview

Lecture Topic
1Interconnects and Scaling
3Ratioed Logic
4Pass Transistor Logic
5Dynamic Logic
6Flipflops and Latches
7Memory Overview
8Design of SRAM Cell

Laboratory Overview

Laboratory Topic
1Decoder Design
2Ratioed Logic
3Pass Transistor Logic
4Dynamic Logic
5Latch and Flipflops
6Memory Array Miscellaneous Components
7SRAM Cell Characterization
8SRAM Cell Modification
9SRAM Column
10SRAM Array
ProjectSRAM Array implemented in GPDK 45nm


AM Session: 8am to 12nn
PM Session: 1pm to 4pm
Day AM/PM Lecture Lab
1AMLecture 1
Lecture 2
Lab 1
PMLecture 3Lab 2
2AMLecture 4Lab 3
PMLecture 5Lab 4
3AMLecture 6Lab 5
PMLecture 7Lab 6
4AMLecture 8Lab 7
PMProjectLab 8
5AMProjectLab 9
PMProjectLab 10


Rico Jossel M. Maestro
University of the Philippines
PIIC Staff
Philippine Institute for Integrated Circuits
Microelectronics and Microprocessors Laboratory
University of the Philippines


  • Marc D. Rosales, University of the Philippines
  • Adelson N. Chua, University of the Philippines
  • Alvionne Sebastian-Baquiran, University of the Philippines
  • John Cris Jardin, University of the Philippines
  • Christian Raymund Roque, Philippine Institute for Integrated Circuits
  • Carlo Capiral, Philippine Institute for Integrated Circuits

Recommended Texts

  • Digital Integrated Circuits: A Design Perspective (2nd Edition) by Jan Rabaey, Anantha Chandrakasan, Borivoje Nikolic